IREFS=0, CLKS=00, IRCLKEN=0, IREFSTEN=0
ICS Control Register 1
| IREFSTEN | Internal Reference Stop Enable 0 (0): Internal reference clock is disabled in stop. 1 (1): Internal reference clock stays enabled in stop if IRCLKEN is set before entering stop. |
| IRCLKEN | Internal Reference Clock Enable 0 (0): ICSIRCLK inactive. 1 (1): ICSIRCLK active. |
| IREFS | Internal Reference Select 0 (0): External reference clock selected. 1 (1): Internal reference clock selected. |
| RDIV | Reference Divider |
| CLKS | Clock Source Select 0 (00): Output of FLL is selected. 1 (01): Internal reference clock is selected. 2 (10): External reference clock is selected. 3 (11): Reserved, defaults to 00. |